Optimized flash memory cell

ABSTRACT

A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate electrodes, a local tungsten interconnect making a substantially continuous connection to the sources. The flash memory is formed by forming floating gate devices, each comprising a floating gate, forming a source electrode for each floating gate device and connecting each source electrode together by a conductive implant into a defined active area, forming a nitride barrier layer overlying each transistor gate, forming a planarized insulation layer over the nitride barrier layer, removing portions of the planarized insulation layer while using the nitride barrier layer to self-align an interconnect via opening to the source electrodes, forming a metal interconnect into the interconnect via, the metal interconnect running a major length of the interconnected source electrodes and making contact therebetween, and forming a metal drain plug for each floating gate device.

This application is a continuation to U.S. patent application Ser. No.09/905,517, filed Jul. 13, 2001 now U.S. Pat. No. 6,706,594.

FIELD OF THE INVENTION

This invention relates to semiconductor fabrication processing and, moreparticularly, to a fabrication method for forming storage cells insemiconductor devices, such as non-volatile flash memory devices.

BACKGROUND OF THE INVENTION

Non-volatile semiconductor memory devices are currently used extensivelythrough the electronics industry. One type of non-volatile semiconductormemory devices employs the use of floating gate memory cells that areable to retain and transfer charge through a variety of mechanisms whichinclude avalanche injection, channel injection, tunneling, etc. A flashmemory device is such a semiconductor device that utilizes a floatinggate memory cell. As is the case with most semiconductors beingfabricated, the industry continues to push for smaller devices thatcontain a larger number of memory cells than each previous generation.This is also the case for the flash memory device.

In a flash memory device, fabrication of the components that make up thefloating gate transistor determines the ability of the device to beprogrammed and retain an electrical charge as well as the ability of thedevice to be reprogrammed by being erased (or the removal of theelectrical charge). Flash memory cells comprising floating gatetransistors are laid out in such a manner that a plurality of cellsforms a memory array.

A device in the programmed state, i.e., charge stored on the floatinggate, represents a stored “0” and a device in the non-programmed state,i.e., no charge stored on the floating gate, represents a stored “1.”Reading a device in the programmed state will cause the device toconduct heavily, while reading a device in the non-programmed state thedevice will not conduct. Each floating gate transistor in the array hasa common source line and the common source line requires sophisticatedfabrication techniques.

The present invention provides a flash memory cell structure and methodto fabricate a floating gate device having a self-aligned floating gate,a low resistant local interconnect to the source and a self-aligneddrain electrode contact plug, all of which will provide enhancedoperation of a flash memory cell device.

SUMMARY OF THE INVENTION

Exemplary implementations of the present invention include a flashmemory device and processes to fabricate a flash memory device.

A first exemplary implementation of the present invention includes aflash memory device comprising a series of floating gate devices eachhaving a floating gate self-aligned to a respective transistor gateelectrode. The sources for each transistor gate are implanted so thatthey are interconnected by a common conductively doped active area. Ametal interconnect runs a major length of interconnected sourceelectrodes and makes substantially continuous contact therebetween. Themetal interconnect may comprise a tungsten-based metal, such astungsten/titanium. A metal self-aligned drain connecting to a respectivedrain may be comprised of tungsten/titanium as well.

A second exemplary implementation of the present invention includesprocess steps for forming a flash memory device on a semiconductorassembly by forming a series of floating gate devices, each havingfloating gate electrodes self-aligned to their respective transistorgate electrode. Implanted source electrodes connected together by aconductively doped active area are formed. Then, a nitride barrier layeris formed such that it overlies each transistor gate. Next, a planarizedinsulation layer is formed over the nitride barrier layer. Portions ofthe planarized insulation layer are removed while using the nitridebarrier layer to self-align an interconnect via to underlying sourceelectrodes.

Next, a metal local interconnect is formed into the interconnect via.The metal interconnect runs the major length of the source electrodes,while making contact therebetween. It is optional to simultaneously formmetal drain plugs for each floating gate device and self-aligning eachmetal drain plug to an underlying drain electrode. The metalinterconnect and the metal drain plug may be formed from atungsten-based metal, such as tungsten/titanium.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top-down view depicting the layout of an array of flashcells, each cell utilizing a self-aligned floating gate,tungsten/titanium local interconnect and a self-aligned drain electrodecontact plug.

FIGS. 2A–2C are cross-sectional views taken through line 1–1′ of FIG. 1after the formation of shallow trench isolation and self-alignedfloating gates.

FIG. 3 is a cross-sectional view taken through line 2–2′ of FIG. 1 afterthe formation of a transistor gate stack for a floating gate device.

FIG. 4 is a cross-sectional view taken through line 3–3′ of FIG. 1 afterthe removal of the shallow trench isolation oxide and an arsenic and/orphosphorous source implant.

FIG. 5 is a cross-sectional view following the cross-sectional view ofFIG. 3 taken after an arsenic and/or phosphorous source implant,followed by an arsenic and/or phosphorous source/drain blanket implant.

FIG. 6 is a cross-sectional view following the cross-sectional view ofFIG. 5 taken after the formation of drain implants, transistor gate capand spacers, followed by the deposition of a conformal layer of nitrideand the formation of a planarized borophosphosilicate glass (BPSG)isolation layer.

FIG. 7 is a cross-sectional view following the cross-sectional view ofFIG. 6 taken after the patterning and etching of contact via opening toexpose the source and drain of the floating gate device.

FIG. 8 is a cross-sectional view following the cross-sectional view ofFIG. 7 taken after the formation of a planarized layer oftungsten/titanium to create self-aligned drain contact plugs and tocreate a tungsten/titanium local interconnect between each source.

FIG. 9 is a cross-sectional view following the cross-sectional view ofFIG. 8 taken after the formation of a planarized layer of inner layerdielectric material that is patterned and etched to provide via openingsto expose the drain contact plugs which is followed by the formation ofa planarized metal to make interconnects between the self-aligned drainplugs.

FIG. 10 is a cross-sectional view following the cross-sectional view ofFIG. 4 taken after the formation of a planarized layer oftungsten/titanium to create a tungsten/titanium local interconnectbetween each source.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary implementations of the present invention directed to processesfor fabricating a floating gate memory device are depicted in FIGS.1–10.

Referring now to the top-down view of FIG. 1, a layout of an optimizedflash cell on wafer substrate 10, is presented. A single flash cell isoutlined by box 11 and is depicted in the subsequent cross-sectionalviews taken through the active areas 20 that define the location of thesource, drain and channel of the floating gate devices to be formed.Shallow trench isolation 25 provides isolation between neighboring gatedevices. Wordlines 34 run horizontally and overlie the self-alignedfloating gates 22. Self-aligned floating gates 22 span betweenself-aligned sources and drains that reside in the confines of activeareas 20. Self-aligned drain contacts 82 make contact to underlyingdrains 51 and tungsten local interconnects 83 make contact to underlyingself-aligned sources 41.

FIGS. 2A–2C are cross-sectional views of FIG. 1 taken through line 1–1′.Referring now to FIG. 2A, Oxide layer 21, polysilicon layer 22 andnitride layer 23 are formed on substrate 10. Material 24, such asphotoresist, is formed to provide a pattern for a subsequentself-aligned floating gate etch and to define active areas 20 andisolation trenches 25.

Referring now to FIG. 2B an etch is performed to create isolationtrenches 25 as well as self-aligned floating gates 22, with patternedgate oxide 21 lying underneath. Patterned nitride 23 overliesself-aligned floating gate 22. Isolation oxide 26 is formed to fillisolation trenches 25, as well as cover the self-aligned source stack ofnitride 23, self-aligned source polysilicon 22 and gate oxide 21.

Referring now to FIG. 2C, isolation oxide 26 is planarized followed bythe removal of patterned nitride 23 (seen in FIG. 2B) to form patternedshallow trench isolation 26 and also to define active areas 20. In thisprocess, floating gate 22 becomes self-aligned to the transistor gate byvirtue of being etched during the shallow trench isolation etch.Optional floating gate wings 27 (seen in overhead view of FIG. 1) mayalso be included.

FIG. 3 is a cross-sectional view of FIG. 1 taken through line 2–2′.Referring now to FIG. 3, various materials have been deposited andetched to form the transistor gate for each floating gate device. Thetransistor gate comprises tunnel oxide 21, a floating gate 22, aninter-polysilicon dielectric (such as an oxide/nitride/oxide stack) 33,polysilicon wordline 34, which is typically capped with tungstensilicide 35 and an oxide or nitride cap 36. It is preferred that adielectric possessing a high dielectric constant of 3 or greater, suchas Al₂O₃ be used for inter-polysilicon dielectric 33. FIG. 3 also showsthe locations of active areas 24.

FIG. 4 is a cross-sectional view taken through line 3–3′ of FIG. 1.Referring now to FIG. 4, an etch (defined as a self-aligned source etchor SAS etch) is performed to remove shallow trench isolation oxide 26(not seen).

FIG. 5 follows the view of FIG. 3. As seen in FIG. 5, photoresist 50 ispatterned and etched to expose underlying silicon 10 prior to asubsequent source implant. Referring now to both FIGS. 4 and 5, anarsenic and/or phosphorous source implant (also defined as aself-aligned source implant or SAS implant) is performed to formself-aligned source region 41, (shown in both FIGS. 4 and 5). Next,photoresist 50 is stripped and a blanket arsenic and/or phosphoroussource/drain implant is performed which simultaneously forms drainregions 51 while also increasing the doping of the source region 41.

It is optional to eliminate both the SAS etch and the SAS implant andrely on the above mentioned subsequent source/drain implant to form thesource and drain conductive regions. If the SAS etch is eliminated,trenches 25 would still contain oxide 26 (as seen in FIG. 2C). If theSAS implant is eliminated, a conventional array oxidation need not beperformed, nor would array source/drain implant drive be necessary.

FIG. 6 follows the view of FIG. 5. Referring now to FIG. 6, transistorisolation spacers 62 are formed. In the present invention, nitride or anoxynitride film is used in order to take advantage of the etchselectivity to oxide. Even though nitride is known to exert more stressthan will oxide on underlying structures and possibly cause electricalchanges, nitride is an effective etch stop material to use during thesubsequently performed self-aligned contact etch. Following theformation of spacers 62, a conformal nitride etch stop barrier layer 63is deposited which will cover source/drain regions 41 and 51 as well ascap 36 and spacers 62.

Nitride layer 63 will function as both an etch stop layer as well as abarrier layer if spacers 62 and caps 36 are formed from oxide. As abarrier layer, nitride layer 63 will prevent the diffusion of dopantatoms into any exposed active areas, such as the source and drainregions. Specifically, nitride layer 63 will prevent boron andphosphorous atoms from diffusing from a subsequently deposited BPSGlayer into the underlying active areas, such as source region 41 anddrain regions 51. Prior to the formation of barrier layer 63, anoptional wet etch may be performed in order to ensure that spacers 62are etched back sufficiently to allow subsequently formed metal (used toform the source and drain interconnects) adequately fill theself-aligned source via openings and the self-aligned drain via openingsthat are etched later in the process. Then the structure is covered withBPSG material 64 that is also planarized.

Referring now to FIG. 7, BPSG material 64 is patterned with photoresist71 to allow for a subsequent via etch (also defined as the self-alignedsource contact etch or a SAS contact etch) to form drain contact viaopenings 72 and source line via opening 73. The via etch removes exposedBPSG material 64 and stops on etch stop barrier layer 63. Next, an etchis performed to clear the conformal nitride from the surface ofsource/drain regions 41 and 51.

Referring now to FIG. 8, photoresist 71 (seen in FIG. 7) is stripped anda conformal titanium nitride barrier layer 81 is deposited along theedges of via openings 72 and 73. Next, a metal such as a tungsten-basedmetal (solely tungsten or titanium tungsten) is formed to fill draincontact via openings 72 and source line opening 73. The metal is thenplanarized to form self-aligned drain contacts 82 (or plugs 82) andlocal interconnect 83 that is self-aligned to source 41. Drain contactplugs 82 will subsequently become connected between the drain ofselected floating gate devices and a digit line.

Referring now to FIG. 9, an inner layer dielectric material 91 is formedover the present structure of FIG. 8. Dielectric material 91 isplanarized and then patterned and etched to form via openings 92 thatexpose underlying drain contact plugs 82. Next a metal 93 is formed thatfills via openings 92. Metal 93 is planarized and serves as a digit linefor the selected floating gate devices.

FIG. 10 is a cross-sectional view taken along the self-aligned source 41of FIG. 1. Referring now to FIG. 10, local interconnect 83 makesconnection to each source of a series of devices that areinner-connected by the self-aligned source implant. Important elementsof the present invention are the combination of using metal localinterconnect 83 with the self-aligned source 41, in conjunction withself-aligned drain contacts 82 (not seen in FIG. 10) that significantlylower source resistance and also allow the fabrication of a smallerfloating gate device. The self-aligned source allows for a smaller cellsimply by its inherent nature of being self-aligned to the transistorgate of each floating gate device. The lowered source resistance, due tothe presence of the metal local interconnect, gives better cellperformance uniformity when comparing the performance of a cell that isrelatively close to a source contact versus a cell fairly far away froma source contact.

By employing the metal local interconnect, the overall size of the arraycan be reduced, as fewer source contacts will be needed compared to aconventional flash cell array. Most importantly, the metal localinterconnect 83 connecting from source to source of series of deviceswill significantly reduce source resistance as the metal (such as atungsten-based metal) provides a much better conducting line than doesthe conductively doped active area that forms the source for eachdevice.

As demonstrated by the teachings of the present invention, the additionof a tungsten/titanium local interconnect to the source electrode, aself-aligned floating gate and a tungsten/titanium self-aligned drainelectrode contact can be efficiently incorporated into conventionalflash memory device fabrication methods.

It is to be understood that although the present invention has beendescribed with reference to several preferred embodiments, variousmodifications, known to those skilled in the art, may be made to theprocess steps presented herein without departing from the invention asrecited in the several claims appended hereto.

1. A method for forming a floating gate memory array comprising: forminga gate dielectric layer on a substrate, wherein the substrate extendshorizontally in perpendicular X and Y directions; forming a floatinggate material layer on the gate dielectric layer; forming a disposablematerial layer on the floating gate material layer; etching columnstrips in the Y direction through the disposable material layer,floating gate material layer and the gate dielectric layer to formisolation trenches into the substrate which extend longitudinally in theY direction; forming an insulator material to a vertical height abovethe disposable material layer; planarizing the insulator material toexpose a top region of the disposable material layer; removing thedisposable material layer to expose a top region of the floating gatematerial layer, wherein the top region of the floating gate materiallayer is recessed below a top surface of the planarized insulatormaterial; forming layers of an intermediate dielectric, a conductivewordline, a tungsten silicide and an insulation cap; etching row stripsin the X direction through the floating gate material layer to a depthof at least the gate dielectric layer to define transistor gates;performing a source implant to form rows of source regions in thesubstrate extending in the X direction in alternate ones of the rowstrips; performing a source/drain implant to simultaneously form drainregions unique to a respective transistor while increasing a doping ofthe rows of source regions; forming dielectric transistor gate spacers;forming a conformal etch stop barrier layer over the transistor gates,the gate spacers, the source regions and the drain regions; forming aplanarized insulation material over the etch stop barrier layer;performing a via etch through the planarized insulation material tocompletely clear the planarized insulation material residing between thetransistor gates, thus exposing the etch stop barrier layer and formingrows of source line vias running in the X direction and separate drainvias unique to each transistor running in the Y direction; clearing ahorizontal component of the conformal etch stop barrier layer thatcovers the source regions and drain regions; and forming individualdrain contacts to a respective transistor gate and rows of sourcecontact interconnects, wherein the individual drain contacts and therows of source contact interconnects substantially fill openings betweenthe transistor gates and abut to a vertical component of the conformaletch stop barrier layer residing on the transistor gates.
 2. A method offorming floating gate transistors comprising: etching isolation trenchesin a Y direction through a layer of floating gate material and tunnelingdielectric, wherein the isolation trenches vertically extend into anunderlying substrate; forming an intermediate dielectric layer and atungsten comprising control gate material layer on the floating gatematerial; etching the control gate, intermediate dielectric layer, andthe floating gate material in an X direction, wherein X is perpendicularto Y, to form individual floating gates from the floating gate materialthat have defined boundaries in the X and Y directions for individualfloating gate transistors, and to form word lines from the control gatematerial having a defined width in the Y direction and extending in theX direction such that multiple transistors spaced apart in the Xdirection share a common word line; implanting common source regionsextending in the X direction such that multiple transistors spaced apartin the X direction share a common source region; implanting drainregions such that transistors spaced apart in the X direction do notshare a common drain region; forming a conformal etch stop barrier layerover the control gates of the common source regions and the drainregions; forming a planarized insulation material over the conformaletch stop layer; performing a via etch through the planarized insulationmaterial to completely clear the planarized insulation material residingbetween the control gates and exposing the etch stop barrier layerthereunder; clearing a horizontal component of the conformal etch stopbarrier layer from the source regions and drain regions; and formingrows of source line contacts running in the X direction to form anelectrical connection to the common source regions; and formingindividual drain contacts to the drain regions; wherein the rows ofsource line contacts and the individual drain contacts substantiallyfill openings between the control gates and abut to a vertical componentof the conformal etch stop barrier layer residing on the control gates.3. A method for forming a flash memory device in a semiconductorassembly, comprising: forming an oxide layer, a polysilicon layer and anitride layer on a silicon substrate; patterning to define active areasand columns of trenches running in a y-direction of the siliconsubstrate; etching the nitride layer, the polysilicon layer and theoxide layer to form the columns of trenches therein and to define gateslocations thereunder; forming oxide to fill the columns of trenches andcover the patterned nitride layer; planarizing the oxide to form columnsof trench isolation running in the y-direction and exposing thepatterned nitride layer; removing the patterned nitride layer to exposethe patterned polysilicon layer; forming transistor gates running in anx-direction of the silicon substrate, the transistor gates comprisingthe patterned oxide, the patterned polysilicon layer, a tunnel oxide, afloating gate, an inter-polysilicon dielectric, a polysilicon wordline,a tungsten silicide and an insulation cap; etching portions of thetrench isolation to form rows of exposed silicon substrate running inthe x-direction; implanting to form rows of source regions self-alignedto the transistor gates, each source region in a common row beingconnected together; implanting to simultaneously form separate drainregions unique to a respective transistor while doping the sourceregions; forming dielectric spacers on the transistor gates; forming aconformal barrier layer over the transistor gates, the dielectricspacers, the source regions and drain regions; forming a planarizedinsulation material over the barrier layer; performing a via etchthrough the planarized insulation material to completely clear theplanarized insulation material residing between the transistor gateslined with the conformal barrier layer, etching to expose an underlyingconformal barrier layer and to simultaneously form rows of source linevias running in the x-direction and separate drain vias unique to eachtransistor; etching to remove a horizontal component of the exposedunderlying barrier layer from the surface of the source regions anddrain regions; forming a titanium nitride layer into the source anddrain vias to make contact with the source regions and drain regionssuch that the titanium nitride layer abuts to a vertical component ofthe conformal barrier layer lining the transistor gates; forming atungsten-based metal into the source and drain vias thus making contactwith the titanium nitride layer; and planarizing the tungsten-basedmetal and the titanium nitride layer to simultaneously form individualdrain contacts self-aligned to a respective transistor gate and rows ofsource interconnects, each row of source interconnects running a majorlength and major width of a respective underlying row of commonlyconnected source regions and making substantially continuous contacttherebetween.
 4. The method of claim 3, wherein said tungsten-basedmetal comprises titanium/tungsten.
 5. A method for forming a flashmemory device in a semiconductor assembly, comprising: on a siliconsubstrate and along a y-axis thereof, forming device isolation separatedby material to define gate locations thereunder; forming transistorgates at the gate locations; removing the device isolation to expose theunderlying silicon substrate at source locations running along an x-axisof the silicon substrate, the removal of the device isolation formingsource locations self-aligned to the transistor gates; implanting intothe exposed underlying silicon substrate to form source regionsself-aligned to the transistor gates and commonly connected together ina row along the x-axis; implanting to simultaneously form drain regionswhile increasing the doping of the source regions; forming a conformaldielectric material over the transistor gates, the source regions andthe drain regions; forming a planarized insulation material over theconformal dielectric layer; performing a via etch through the planarizedinsulation material to completely clear the planarized insulationmaterial residing between the transistor gates lined with the conformaldielectric material, forming source and drain openings in the byclearing a horizontal component of the conformal dielectric material toexpose the source regions and the drain regions; forming metal into thesource and drain via openings to make contact with the source regionsand the drain regions such that the metal substantially fills the viaopenings and abuts to a vertical component of the conformal dielectricmaterial lining the transistor gates; and planarizing the metal tosimultaneously form individual drain contacts self-aligned to arespective transistor gate and a row of source interconnects, each rowof source interconnects running a major length and major width of arespective underlying row of commonly connected together source regionsand making substantially continuous contact therebetween.
 6. The methodof claim 5, wherein said tungsten-based metal comprisestitanium/tungsten.